Creato da
Share My Page
My Social Accounts
Account FaceBook Account LinkedIn Account Twitter Account Google Plus Account Git Hub

The memories are working at a different frequency than that of the Host BUS. To ensure that the memories not slow down the system is necessary to adopt solutions of different types both from the technological point of viewboth architectural (interleaving).

Also if you use dynamic memory must consider the time to refresh and detection / correction of errors.
Interleaving is the decision to implement the dynamic memory in blocks with the same parallelism andmapping addresses sequentially between adjacent desks.This makes it possible to preload a table adjacent, whileanother is being accessed.
Usually communicate with the DRAM cache and moveblocks of contiguous memory.
E 'for this reason that they are organized in matrix formwhere at each intersection of row and column is a capacitor, which has the task of storing one bit, and a transistor, that enables him.
To read the contents of a cell is necessary to open the transistor, so that the bit is being carried on the line of the column. The selection of the cell takes place by enabling the corresponding row and column desired. Half of the addresses (ABUS / 2) selecting the row, while the remaining part of the column select addresses. Contiguouselements of a row are adjacent in the logical sense.

Average (1 Vote)
The average rating is 5.0 stars out of 5.