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is a mechanism that allows certain hardware subsystemsof a computer (peripherals) to directly access system memory to exchange data, or read or write, without involving the CPU.
It presents cycles BUS, in order to manage priority andarbitration of the bus. The communication protocolprovides for the transfer and also the ACK hardware.
The cycle of DMA bus is divided into phases depending on the function. Without DMA in the case of a transfer ofdata between memory and peripheral:

-The memory is read by placing sull'Address BUS address and with the signal of MEMR.
A peripheral-BUS sull'Address is written by putting the address and with the signal IOW.

With DMA operations are condensed. In fact the memory is selected by the ABUS and MEMR, while the peripheral is selected by IOW at the same instant.
Each DMA channel contains:
-16 bit-address register, the remaining bits of an addressbus (upper address) are contained in the Page registers.
- cycle counter 16 bit

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