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Depending on the system under analysis, there are different configurations of the bus. In general we can say that in a PC BUS there are different at different speeds.They are organized as a hierarchy from the faster (closest to the processor), the slower (closer to the devices).

To connect the different levels of the bus there are species of routers, said bridge, with the task of sorting the packets (conversion).
In practice there are two main desktop system into a bridge:
North-Bridge, which handles the dynamic memory (RAM, cache, VGA). The fact that RAM and cache are on the same bus, implies that they can not exchange data directly, but only when the bus is not occupied by the processor.
South-Bridge, which communicates with the NorthBridge and manages a number of interfaces (USB, IDE, Serial ATA).

Normally these two bridges is also aligned the Super I / O interfaces that communicate with the older.
The performance of a BUS therefore depends not only on the parallelism of the data bus (DBUS) and from the clock, but also by the speed of the devices that use it.
For example, the PCI bus devices face only consistent with his speed, while the slower ones facing the ISA (available via a DMA).

With regard to systems Server they have a higher number of cache levels, connected directly to the processor or the RAM. The processor then communicates via a bridge to the BUS system and by other bridges to the LAN interfaces.

The ability to transfer BUS is expressed in MBps (megabytes per second). The number of bits of DBUS, which communicates with the cache is much greater than the number of bits with which the processor works.
In fact, these bits are used for the updating of the cache, not in the normal operation of the CPU. For example, in the IA-32 BUS is not 32bit, but it has more.


The main signals for the management of the system bus are:

KEN-indicates that the cycle is cacheble
Brdy-shows if the device has completed addressed access in Burst Mode
-R / W cycle of a read / write
-C / D indicates whether it is or Date Code
IO / M indicates whether you are communicating with a device I / O or a memory
LOCK-indicates that the current bus cycle is taking place with LOCK prefix instruction. Consequently, the bus can not be used by another potential master.

The communication signals with the DMA controller are:
-HOLD indicates that a device wants to use DMA.
-HLDA is activated to indicate that the communication is ready.

The communication signals with the interrupt controller are:
INTR-(in) an interrupt request from an external device.
INTA-(out) interrupt request accepted and timing of the transfer of the interrupt code.
NMI non-maskable interrupt.

The communication signals with the Address Bus are:
-ADS signal during the first clock pulse signals that an address is ready sull'Address BUS. Defines the beginning of a bus cycle and allow all the devices that look out on the bus to synchronize.

The communication signals with the Data BUS are:
READY-synchronize the CPU to the outside. If WAIT is active instruction the CPU waits until READY is not active before the next statement.
-D63: D0 data lines

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