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The processor performs two main tasks: carry out the instructions and interacts with the outside world. Each instruction is composed of two phases:

Fetch: the code is picked up and read from memory
Execute: the code is decoded and executed.
The execution of each instruction involves the initiation of some microinstructions, each of which is executable in a precisely TCPU. The number of registers greatly influences the execution time of each instruction, if they are talking about many register-file.
CISC (IBM 370), with a set of instructions increasinglylarge and complex, capable of reaching almost the high-level languages??. The instructions are not faster because they require complex hardware. They have a longlatency for interrupt more.
RISC (Motorola 80000, SPARC, PowerPC, ARM 7.9), with a reduced instruction set very high number of pipelineregisters, and a particularly optimized (an operation toblow CK). The RISC instructions are complex as those CISC and therefore can be realized with the technique ofmicro-programmed. There are only two instructionswhich involve the primary memory (LOAD and STORE)and thus may be particularly optimized and will be the only ones to provide mechanisms for specifying the address in memory to be accessed (a few methods ofaddressing).
The superscalar processors are able to complete more than one instruction per stroke of CK. Internally contain a pipeline similar to that of RISC, only a few stages correspond more units in parallel. The units in parallel can perform the same operations, or have other purposes.Problems arise in case of emergency.
The adoption of the pipeline aims to improve the performance of a processor by changing the architectureof the same. With the introduction of the pipeline, if at full capacity, the RISC can produce a result for each clock pulse, while superscalar perform multiple operations per shot clock.
Between one stage and the next there is a buffer in order to give rhythm operations. Very often each stage takes more than a shot clock, then you are in a stalemate: a stadium can not find the next free buffer to be written and then is forced to stop, blocking all upstream stages, thosevalley can continue to work but there is a loss ofperformance and creating a bubble of inactivity. The main causes of stalling are some of the slow loading and writing or execution of some tasks difficult to accomplish.The slowness of loadings is in part arginabile with the use of cache very fast and reliable.
When you have an operation longer than expected tofetch the entire pipeline is blocked, then to try to decrease the chance that this is realized, the buffer interposedbetween the fetch and decode is structured as a FIFO queue.
To prevent the formation of errors it is necessary thatmore data that are processed in parallel in the samepipeline have no dependence between them
Here there are the mainly stages:
- Fetch the instruction is loaded
- Decode the instruction is decoded and are activated the corresponding control signals and taken operands
- Operate, the statement is executed
- Write, the result is saved
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