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A subsystem of I / 0 is composed of:

  • Peripherals
  • Unit to control these devices
  • Software for management


Each device is associated with a specific interface that connects to the bus.

There are several ways to organize the address space of the devices:

  • Isolated I / O address space is independent of the data.Appropriate bits distinguish the two types of addresses. So there are special commands to manage devices (IN, OUT).8086
  • Memory Mapped I / O address space is shared with that data. Some areas of the same memory can therefore be used to store data, but only to pass them to the devices. In this way to send a given to a device one can use the standard instructions (MOV for example). Motorola 68000


The speed of reading and writing devices, I / O is very often very different to that of the CPU, as will often have to interface with the outside world. There are various ways to manage synchronization:

  • Programmed I / O. Device management is totally dependent on the CPU. The displacement of each data implies an operation by the CPU. When I / O is based on performing a test on the state register, to understand when you can go further, says poll. This method is inexpensive and not very efficient since the CPU must perform a series of checks unnecessary, all the data passes through the CPU.
  • Interrupt
  • Direct Memory Access (DMA). In this case the management is entrusted to a circuitry external to the CPU, said DMA. It is to worry about managing the BUS.For each peripheral DMA has several lines (Acknowledge, demand, control) and registers (DC IOAR). Management by DMA takes place in several steps: the CPU loads into DC and IOAR, the address from which to start the operation and the number of data to be processed and informs on a bit if it is a read or write. The DMA receives a request for intervention by a DMA device and sends a Request to the CPU. When the CPU checks the Request bit is active and stops and activates the signal Acknowledge and start the transfer. At each step is incremented and decremented IOAR DC until DC is not equal to 0. The transfer between DMA and I / O can occur in several ways:
    •      A blocks (burst transfer). It provides that once it starts the DMA transfer does not leave control of the bus to the CPU, till it is finished. The CPU remains blocked throughout the transfer.
    •      Cycle or stealing. The blocks are small in size, in this way the time in which the CPU is locked is more fremmentato
    •      Transparent or DMA. The DMA takes the bus when the CPU does not need it.
  • Processors I / O.


There are several ways to serve the requests by devices of attention to the CPU:

  • Polling. The CPU carries out a periodic check on all the devices, one at a time. If any of them has applied the device is being served. This method is simple to implement, but has a high latency as well as lead to many polls with answers always negative.
  • Interrupt. It 's based on the presence of an asynchronous signal, the device sends to the CPU in case of need. In this way, the latency time is minimal and there is no loss of time by the CPU to carry out controls.


To handle multiple concurrent requests using different strategies:

  • Lines of multiple interrupts. In this solution, each device is associated with a own leg for interrupt handling. This is impractical because the devices are in very high number.
  • Polling. At the moment when the foot is intended interrupt is triggered, the CPU scans all the elements that can having made a request, until it is found. Increases latency. Depending on the order in which the checks are done changing priorities.
  • Vectored interrupts. There is a special device called Interrupt Controller (IRQ), which has the task to send an interrupt signal to the CPU whenever the CPU is able to respond, and puts on the BUS an identification code to a service procedure contained in ' Interupt vector table.Usually this table is located at the front of main memory.The IRQ manages priorities.
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